Silicon Interfaces' BBP core for Wireless LAN is
compatible with 802.11 a b and g IEEE standards. BBP is a PHY entity for an OFDM and DSSS, aimed for data transfer rates upto 54 Mbps at the unlicensed frequency range of 2.4 and 5 GHz. This specification describes the functions of the signal processing in the medium and the interface with the radio.
BBP Core is designed to be used at higher speeds providing maximum performance with minimum power consumption. High decode gain Viterbi algorithm for added performance. The baseband processor can interface to an RF using either an analog I/Q interface or a digital interface....view full
Wireless LAN (MAC)
Silicon Interfaces' MAC
core for Wireless LAN is compatible with 802.11 a b and g IEEE Standards. It is designed to handle packetized DSSS transmissions; the software implementation supports all Data Rates. The MAC Management or Control Functionality is implemented in hardware.SI24WLAN11 is designed to use at higher speeds providing maximum performance with minimum power consumption, without draining the device batteries....view full
The iW-PCIe to ISA Bridge consists of a single ISA
bus controller & a Xilinx endpoint core for PCIe with PHY interface. The PCIe bridge is a 32 bit PCI express interface that fits into a single Spartan3 FPGA....view full
The iW-PCIe to UART Bridge consists of a single
UART controller & a Xilinx endpoint core for PCIe with PHY interface. The PCIe to UART bridge is a 32 bit PCI express interface that fits into a single Spartan3 FPGA...view full
SPI-4 is an interface for packet and cell transfer
between a physical layer (PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet applications.
eInfochips’s SPI4.2 Interface IP is a configurable and an efficient implementation. It is fully compliant to Optical Internetworking forum’s OIF-SPI-4-02.1, System packet interface Level 4 Phase 2 implementation agreement....view full
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