This high performance, fully programmable Reed
Solomon Decoder IP Core is intended for use in a wide range of applications requiring forward error correction and can be targeted in any ASIC or FPGA technologies.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system is strongly depended on the amount of redundancy as well as on the coding algorithm itself....view full
This high performance, fully configurable Reed
Solomon Encoder IP Core is intended for use in a wide range of applications requiring forward error correction and can be targeted in any ASIC or FPGA technologies. In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used for channel noise elimination....view full
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