The MXL-SRDS-EPON is an Ethernet Passive Optical
Network (EPON) transceiver implemented in digital CMOS technology. The SerDes IP offers data transfer rate of 1.25Gbps, for both upstream & downstream direction, meeting IEEE 802.3ah EPON standard specification.
The receiver side implements programmable post equalization, with on chip terminations, clock/data recovery PLL and De-Serializer. The Serializer section uses the recovered clock to serialize the parallel data to be transmitted. The transmitter then drives the serial data on the serial differential outputs, while incorporating the pre-emphasis signal.
The MXL-SRDS-EPON is capable of generating low-jitter outputs in the noisy environment typical of million-gate SOC....view full
The MXL-LVDS-RX-4CH is a high performance
4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 180MHz. The Receiver is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the receiver margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design....view full
The MXL-PHY-MIPI is a high-frequency low-power,
low cost, source-synchronous, physical layer compliant with the MIPI Alliance Standard for D-PHY. Although it is primarily used for connecting cameras and display devices to a cost processor, it can also be used for many other portable applications. It is used in a master-slave configuration. High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control....view full
The MXL-LVDS-TX-4CH is a high performance
4-channel LVDS Transmitter implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 180MHz. The transmitter is highly integrated and requires no external components. It employs optional preemphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design....view full
The MXL-PLL-MIPI-PXL is a high performance PLL
based frequency synthesizer implemented using digital CMOS technology. It is highly integrated and requires no external components. Differential circuit techniques are employed to attain low jitter in the noisy environment typical of multi-million gates digital chip.
The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design. The MXL-PLL-MIPI-PXL incorporates a Lock Detector, three programmable output dividers, and supports a full-power down mode....view full
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