The GEMAC (Gigabit Ethernet Media Access
Controller) core implements the Ethernet Media Access Control (MAC) protocol according to IEEE 802.3 specification. The MAC has a standard Gigabit Media Independent Interface (GMII) to connect to any PHY interface. The complete modular design of the cores facilitates easy customization to include value added and distinguishing features.
The GEMAC implements half duplex functions such as Carrier Extension and Packet Bursting. In full duplex mode, the GEMAC implements both symmetrical and asymmetrical flow control via IEEE 802.3x Pause MAC Control frames. Pause frames can be generated according to flow control thresholds within the on-chip receive FIFO....view full
This core is a highly integrated Bluetooth
baseBand controller designed to form the heart of Bluetooth wireless communication systems.The SI23BTB20 Bluetooth baseband Controller implements EDR(Enhanced Data Rate) operation as defined under the Bluetooth 2.0 specifications. It implements baseband and host controller interface (HCI) of the Bluetooth protocol and is specifically designed to meet the immediate market needs for low-power Bluetooth applications. The on-chip peripherals provide easy interfacing to a Bluetooth radio and to a host system....view full
Silicon Interfaces USB 2.0 function controller is
a highly integrated USB solution for USB applications. It simplifies the design of the USB systems and reduces the time to market. The SI16USB20 is a USB Function controller core designed as per USB 2.0 revision of USB standards. This core provides
480Mb/s high speed USB interface. It autonomously handles the USB transactions and data transfers, thus bridging the USB interface to an easy read / write parallel interface. It has the standard UTMI interface at host end and a generic 8-bit Microcontroller Interface at the device end....view full
USB OTG Function Controller is a highly integrated
USB OTG solution for USB OTG applications. SI22USBOTG11 is a USB OTG Function Controller Core designed as per USB OTG specification, which is a supplement to USB 2.0 specification. It has the standard UTM+ Interface at Host end and a generic
Microcontroller Interface at the Device end. SI22USBOTG11 is user-configurable and individually programmable for Bulk/Interrupt or Isochronous transfers. It operates either as a Function Controller for a USB peripheral or as the Host / Peripheral in point-to-point communication with another USB Function...view full
Silicon Interfaces link layer core is a functional
block available for insertion into a customer's ASIC design, which supports the IEEE 1394a-2000 Draft specifications for a high-speed serial bus. SI16FWA20, 1394a-2000 link layer Controller Core provides data packet delivery service for Asynchronous and Isochronous (real-time) data transmission. It performs arbitration request, packet generation and checking as well as data and acknowledgement transmission....view full
The SI40U550 IP core is a Universal Asynchronous
Receiver Transmitter fully compatible with the de-facto standard 16550 UART. The SI40U550 core performs serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from the host . The host can read the UART status at any time. The SI40U550 core includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link....view full
The SI 79C90 interfaces a minicomputer or
microcomputer with the IEEE 802.3 / Ethernet Local Area Network. Its versatile bus interface logic interfaces the peripheral chip with Intel, Motorola, Zilog or AMD microprocessors. The serial I/O interface is compatible with Ethernet IEEE 802.3 draft specifications. On-board DMA, advanced buffer management, and extensive error reporting and diagnostics facilitate design and improve system performance....view full
Silicon Interfaces' STS-1/3 framer is a single
core solution incorporating Synchronous Optical Network / Synchronous Digital Hierarchy (SONET / SDH) protocol as per ANSI and ITU standards. This significantly reduces the cost of implementing complex SONET / SDH System Designs.SONET carries low speed digital signals such as DS1, DS2 and DS3 to form the basic building block called Synchronous Transport Signal (STS-1). It operates at the base bandwidth of 51.84 Mbps. frame rate is 8000 frames per second....view full
Silicon Interfaces' core for Wireless LAN is
compatible
with 802.11 a b and g IEEE Standards. It is designed to handle
packetized DSSS (Direct Sequence Spread Spectrum) and
OFDM (Orthogonal Frequency Division Multiplexing) data
transmissions; the software implementation supports all data
rates. The MAC management or control functionality is
implemented in firmware while the time critical functionality
is implemented in hardware....view full
You need to either login or register as a buyer or seller to view more IP information
